发明名称 Method of manufacturing semiconductor device using stress memorization technique
摘要 The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.
申请公布号 US8772095(B2) 申请公布日期 2014.07.08
申请号 US201213495062 申请日期 2012.06.13
申请人 Samsung Electronics Co., Ltd. 发明人 Kim Seok-Hoon;Kim Sang-Su;Koh Chung-Geun;Lee Sun-Ghil;Joe Jin-Yeong
分类号 H01L21/00 主分类号 H01L21/00
代理机构 Volentine & Whitt, PLLC 代理人 Volentine & Whitt, PLLC
主权项 1. A method of manufacturing a semiconductor device, the method comprising: providing a structure that includes a substrate, and a gate electrode at an upper part of the substrate, the gate electrode having opposite sides; forming doped amorphous source/drain regions to the sides of the gate electrode, respectively, such that the amorphous source/drain regions are spaced from each other across a channel region of the substrate; subsequently annealing the substrate to recrystalize the doped amorphous source/drain regions; and before the substrate is annealed, forming over the doped amorphous source/drain regions of the substrate a stress inducing layer that stresses the doped amorphous source/drain regions during the recrystallizating of the doped amorphous source/drain regions, and wherein the forming of the doped amorphous source/drain regions comprises a pre-amorphization implantation (PAI) process that amorphizes the source/drain regions to the sides of the gate electrode, and implanting, into the amorphized source/drain regions, impurities that will minimize differences between crystal growth rates in different crystallographic directions during the annealing of the substrate.
地址 Suwon-si, Gyeonggi-do KR