发明名称 |
Semiconductor memory device |
摘要 |
A semiconductor memory device includes a semiconductor film; a first gate insulating film covering the semiconductor film; a first gate electrode provided over the semiconductor film with the first gate insulating film interposed therebetween; a first conductive film which is provided over the first gate insulating film; an insulating film which is provided over the first gate insulating film, exposes top surfaces of the first gate electrode and the first conductive film, and has a groove portion between the first gate electrode and the first conductive film; an oxide semiconductor film which is provided over the insulating film and is in contact with the first gate electrode, the first conductive film, and the groove portion; a second gate insulating film covering the oxide semiconductor film; and a second gate electrode provided over the oxide semiconductor film and the groove portion with the second gate insulating film interposed therebetween. |
申请公布号 |
US8772849(B2) |
申请公布日期 |
2014.07.08 |
申请号 |
US201213410608 |
申请日期 |
2012.03.02 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
Noda Kosei |
分类号 |
H01L29/76;H01L29/12 |
主分类号 |
H01L29/76 |
代理机构 |
Robinson Intellectual Property Law Office, P.C. |
代理人 |
Robinson Eric J.;Robinson Intellectual Property Law Office, P.C. |
主权项 |
1. A semiconductor memory device comprising:
a semiconductor layer; a first gate insulating layer over the semiconductor layer; an insulating layer over the first gate insulating layer; a first gate electrode over the semiconductor layer with the first gate insulating layer interposed therebetween, wherein the first gate electrode is provided in the insulating layer; a conductive layer provided in the insulating layer; an oxide semiconductor layer in contact with the first gate electrode, the conductive layer, and side surfaces of a groove portion in the insulating layer; a second gate insulating layer covering the oxide semiconductor layer; and a second gate electrode provided over the oxide semiconductor layer with the second gate insulating layer interposed therebetween. |
地址 |
Atsugi-shi, Kanagawa-ken JP |