发明名称 |
Signal processing circuitry with frontend and backend circuitry controlled by separate clocks |
摘要 |
An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate. |
申请公布号 |
US8773799(B1) |
申请公布日期 |
2014.07.08 |
申请号 |
US201213724946 |
申请日期 |
2012.12.21 |
申请人 |
LSI Corporation |
发明人 |
Tedja Suharli;Yang Shaohua;Zhang Fan;Zuo Qi;Garofalo Joseph;Kou Yu |
分类号 |
G11B5/09 |
主分类号 |
G11B5/09 |
代理机构 |
Ryan, Mason & Lewis, LLP |
代理人 |
Ryan, Mason & Lewis, LLP |
主权项 |
1. An apparatus, comprising:
read channel circuitry; and signal processing circuitry associated with the read channel circuitry, the signal processing circuitry comprising: frontend processing circuitry comprising a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal; backend processing circuitry comprising a backend detector, an interleaver, a backend decoder, and a de-interleaver, the backend processing circuitry being configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal; wherein the frontend processing circuitry is controlled by a first clock having an associated first clock rate and wherein the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate, the second clock rate being determined at least in part by the first clock rate and a maximum clock rate. |
地址 |
San Jose CA US |