Extracting clock information from a serial communications bus for use in RF communications circuitry

摘要

The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signals. The clock information may be associated with one or more serial communications commands via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both.

主权项

1. Circuitry comprising:
a first radio frequency front-end (RFFE) circuit coupled to an RFFE serial communications bus and adapted to during a non-communications operating mode:
extract clock information from the RFFE serial communications bus; andgenerate a first clock signal based on the clock information; and at least a second RFFE circuit, such that each of the at least the second RFFE circuit is coupled to the RFFE serial communications bus, and during a communications operating mode, at least the second RFFE circuit is adapted to react to at least one of a plurality of commands from the RFFE serial communications bus.