Package for three dimensional integrated circuit

摘要

A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

主权项

1. A device comprising:
a semiconductor substrate having a recess portion and a non-recess portion, wherein a first recess is located at the recess portion; an isolation layer formed on the non-recess portion of the semiconductor substrate; a redistribution layer formed on the isolation layer; an under bump metal structure formed on the redistribution layer; and a first bump formed on the under bump metal structure.