Duty cycle correction circuit

摘要

A duty cycle correction circuit comprises a duty cycle detector, a filter, a comparator, a SAR DAC, an equalization device, a pass gate circuit, and a duty cycle corrector. The duty cycle detector generates control signals in response to internal clock signals. The equalization device equalizes voltage levels of the control signals, and the pass gate circuit applies the control signals to the duty cycle corrector. The filter obtains average voltages of the control signals. The comparator compares output signals from the filter to generate a comparison result. The SAR DAC performs a SAR algorithm to generate analog output signals based on the comparison result. The duty cycle corrector receives external clock signals, the analog output signals, and output signals from the pass gate circuit to generate the internal clock signals with a corrected duty cycle.

主权项

1. A duty cycle correction circuit, comprising:
a duty cycle detector configured to generate a pair of control signals in response to a pair of internal clock signals; a filter configured to obtain average voltages of the pair of control signals; a comparator configured to compare a pair of output signals from the filter to generate a comparison result; a successive approximation register digital to analog converter (SAR DAC) configured to perform a SAR algorithm to generate a pair of analog output signals based on the comparison result; a first equalization device configured to equalize voltage levels of the pair of control signals; a pass gate circuit configured to apply the pair of control signals to a duty cycle corrector if the pass gate circuit is enabled; and a duty cycle corrector configured to receive a pair of external clock signals, the pair of analog output signals, and a pair of output signals from the pass gate circuit to generate the pair of internal clock signals with a corrected duty cycle.