发明名称 | Fractional PLL circuit | ||
摘要 | A fractional PLL circuit includes: a phase comparator for detecting a phase difference, and which outputs a controlled voltage; a voltage-controlled oscillator for generating and outputting an output clock signal; a phase-selection circuit for selecting any one of a predetermined number of phases into which one period of a clock of the output clock signal is equally divided, generating a phase-shift clock signal having a rising edge in the selected phase, and outputting the phase-shift clock signal to the phase comparator; and a phase controller for determining a phase of the rising edge of the phase-shift clock signal selected by the phase-selection circuit such that a period of the phase-shift clock signal is a length that is changed by a predetermined phase-shift amount from a period of the output clock signal, and controlling the phase-selection circuit so as to select the determined phase. | ||
申请公布号 | US8773183(B2) | 申请公布日期 | 2014.07.08 |
申请号 | US201214004967 | 申请日期 | 2012.03.12 |
申请人 | Ricoh Company, Ltd. | 发明人 | Watabe Yuji;Kanno Tohru |
分类号 | H03L7/06 | 主分类号 | H03L7/06 |
代理机构 | Cooper & Dunham LLP | 代理人 | Cooper & Dunham LLP |
主权项 | 1. A fractional PLL circuit comprising: a phase comparator that detects phase difference between an input clock signal that is a reference and a feedback signal, and outputs a controlled voltage in accordance with the phase difference; a voltage-controlled oscillator that generates and outputs an output clock signal that has a frequency based on the controlled voltage; a phase-selection circuit that selects any one of a predetermined number of phases into which one period of a clock of the output clock signal is equally divided, generates a phase-shift clock signal that has a rising edge in the selected phase, and outputs the phase-shift clock signal as the feedback signal to the phase comparator; and a phase controller that determines a phase of the rising edge of the phase-shift clock signal selected by the phase-selection circuit such that a period of the phase-shift clock signal is a length that is changed by a predetermined phase-shift amount from a period of the output clock signal, and controls the phase-selection circuit so as to select the determined phase. | ||
地址 | Tokyo JP |