发明名称 High voltage high side DMOS and the method for forming thereof
摘要 A high voltage high side DMOS removing the N-buried layer from the DMOS bottom provides lower Ron*A at given breakdown voltage. The high voltage high side DMOS has a P-type substrate, an epitaxial layer, a field oxide, an N-type well region a gate oxide, a gate poly, a P-type base region, a deep P-type region, an N-type lightly doped well region, a first N-type highly doped region, a second N-type highly doped region and a P-type highly doped region.
申请公布号 US8772867(B2) 申请公布日期 2014.07.08
申请号 US201213692984 申请日期 2012.12.03
申请人 发明人 Yoo Ji-Hyoung;Garnett Martin E.
分类号 H01L29/66 主分类号 H01L29/66
代理机构 Perkins Coie LLP 代理人 Perkins Coie LLP
主权项 1. A high voltage high side DMOS, comprising: a P-type substrate with an epitaxial layer formed on the P-type substrate; a field oxide formed on the epitaxial layer; an N-type well region formed in the epitaxial layer; a gate oxide formed on the epitaxial layer; a gate poly formed on the gate oxide and on the field oxide; a P-type base region formed in the epitaxial layer; a deep P-type region merging with the P-type base region formed in the epitaxial layer; an N-type lightly doped well region formed under the P-type base region in the epitaxial layer, wherein the N-type well region is formed in the N-type lightly doped well region; a first N-type highly doped region formed in the N-type well region; a second N-type highly doped region formed in the P-type base region; a P-type highly doped region formed in the P-type base region, the P-type highly doped region being adjacent to the second N-type highly doped region; a TEOS layer formed on the gate poly; an inter layer dielectric formed on the TEOS layer and on the gate oxide; a drain electrode contacted with the first N-type highly doped region; and a source electrode contacted with both the second N-type highly doped region and the P-type highly doped region.
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