Array substrate structure of display panel and method of making the same

摘要

An array substrate structure of a display panel includes a substrate, a plurality of first wirings, a first patterned insulating layer, a plurality of second wirings, a plurality of first protective patterns, and a plurality of second protective patterns. The substrate has a wiring region. The first wirings are disposed in the wiring region. The first patterned insulating layer is disposed on the first wirings. The second wirings are disposed on the first patterned insulating layer. The first protective patterns are disposed in the wiring region and disposed on the corresponding second wiring, respectively, where the first protective pattern includes a semiconductor material. The second protective patterns are disposed on the corresponding first protective pattern, respectively, where the second protective pattern includes an inorganic insulating material.

主权项

1. A method for forming an array substrate structure of a display panel, comprising:
providing a substrate having a display region and a wiring region; forming a first patterned conductive layer on the substrate, the first patterned conductive layer comprising:
a plurality of gate lines disposed in the display region;a plurality of gate electrodes disposed in the display region; anda plurality of first gate tracking lines disposed in the wiring region, the first gate tracking lines being electrically connected to a portion of the gate lines; forming a first patterned insulating layer on the first patterned conductive layer, the first patterned insulating layer having a plurality of first contact holes respectively exposing a portion of the gate lines; forming a second patterned conductive layer on the first patterned insulating layer, the second patterned conductive layer comprising:
a plurality of data lines disposed in the display region;a plurality of source electrodes and a plurality drain electrodes disposed in the display region; anda plurality of second gate tracking lines electrically connected to the exposed portions of the gate lines through the first contact holes; forming a patterned semiconductor layer and a second patterned insulating layer on the second patterned conductive layer, the patterned semiconductor layer comprising a plurality of semiconductor channel layers and a plurality of first protective patterns, the semiconductor channel layers being disposed in the display region and disposed on the corresponding gate electrodes, at least a portion of the first protective patterns being disposed in the wiring region and disposed on the corresponding second gate tracking lines, the second patterned insulating layer comprising a plurality of channel protective layers and a plurality of second protective patterns, the channel protective layers being disposed in the display region and disposed on the corresponding semiconductor channel layers, at least a portion of the second protective patterns being disposed in the wiring region and disposed respectively on the corresponding first protective patterns; forming a first patterned protective layer and a second patterned protective layer on the second patterned conductive layer, the first patterned protective layer and the second patterned protective layer exposing each of the second protective patterns, and the first patterned protective layer and the second patterned protective layer having a plurality of second contact holes respectively exposing the drain electrodes; and forming a first patterned transparent conductive layer on the second patterned protective layer.