发明名称 VALID PROCESSOR CORE ARRANGEMENT DEVICE, VALID PROCESSOR CORE ARRANGEMENT METHOD AND VALID PROCESSOR CORE ARRANGEMENT PROGRAM
摘要 <p>PROBLEM TO BE SOLVED: To provide a valid processor core arrangement device capable of optimally arranging a valid processor core on the basis of a condition designated by a user.SOLUTION: A valid processor core arrangement device 1 comprises: one or more processors including one or more processor cores; a display unit 5 for displaying a valid processor core setting screen in which the maximum number of processor sockets and the maximum number of processor cores are input; and a control unit 4 for, on the basis of the maximum number of processor sockets and the maximum number of processor cores which are input in the display unit 5, determining a valid processor and a valid processor core.</p>
申请公布号 JP2014127059(A) 申请公布日期 2014.07.07
申请号 JP20120283933 申请日期 2012.12.27
申请人 NEC CORP 发明人 HOSHINO TOMONORI
分类号 G06F15/177 主分类号 G06F15/177
代理机构 代理人
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