| 发明名称 |
APPARATUS AND METHOD FOR A HYBRID LATENCY-THROUGHPUT PROCESSOR |
| 摘要 |
An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic. |
| 申请公布号 |
US2014189317(A1) |
申请公布日期 |
2014.07.03 |
| 申请号 |
US201213730055 |
申请日期 |
2012.12.28 |
| 申请人 |
Ben-Kiki Oren;Yosef Yuval;Pardo Ilan;Markovich Dror |
发明人 |
Ben-Kiki Oren;Yosef Yuval;Pardo Ilan;Markovich Dror |
| 分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
| 代理机构 |
|
代理人 |
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| 主权项 |
1. A processor comprising:
latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic. |
| 地址 |
Tel-Aviv IL |
