| 发明名称 |
METHOD AND APPARATUS FOR STORING DATA |
| 摘要 |
A memory system (1) comprising a control logic (2) adapted to receive a number n of write requests (WRs) from input ports and to receive a read request (RR) from an output port within a clock cycle of a clock signal (CLK) applied to said memory system (1), wherein n is a natural number; and n+1 memory banks (4) of a shared memory (3) adapted to store data, wherein the control logic (2) is adapted to control a memory bank occupancy level MBOL of each memory bank (4) such that the differences between memory bank occupancy levels MBOLs of the memory banks (4) are minimized |
| 申请公布号 |
US2014185368(A1) |
申请公布日期 |
2014.07.03 |
| 申请号 |
US201414198195 |
申请日期 |
2014.03.05 |
| 申请人 |
Huawei Technologies Co., Ltd. |
发明人 |
ZECHARIA Rami;SHACHAR Yaron |
| 分类号 |
G11C11/413 |
主分类号 |
G11C11/413 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory system (1) comprising:
a control logic (2) adapted to receive a number n of write requests (WRs) from input ports and to receive a read request (RR) from an output port within a clock cycle of a clock signal (CLK) applied to said memory system (1), wherein n is a natural number; and n+1 memory banks (4) of a shared memory (3) adapted to store data, wherein the control logic (2) is adapted to control a memory bank occupancy level, MBOL, of each memory bank (4) such that the differences between memory bank occupancy levels, MBOLs, of the memory banks (4) are minimized |
| 地址 |
Shenzhen CN |
