| 发明名称 |
BLOCK-LEVEL SLEEP LOGIC |
| 摘要 |
In one embodiment, a processor includes at least one sleep block and a central sleep controller. The at least one sleep block may include at least one execution unit, at least one processor component, and sleep logic. The central sleep controller may be to program the sleep logic to perform at least one sleep transition for the at least one sleep block, and to operate in a first sleep mode. The sleep logic may be to perform the at least one sleep transition for the at least one sleep block without waking the central sleep controller from the first sleep mode. Other embodiments are described and claimed. |
| 申请公布号 |
US2014189401(A1) |
申请公布日期 |
2014.07.03 |
| 申请号 |
US201213729376 |
申请日期 |
2012.12.28 |
| 申请人 |
KEPPEL DAVID PARDO;NASRULLAH JAWAD JAKE |
发明人 |
KEPPEL DAVID PARDO;NASRULLAH JAWAD JAKE |
| 分类号 |
G06F1/32 |
主分类号 |
G06F1/32 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A processor comprising:
at least one sleep block, including:
at least one execution unit;at least one processor component;sleep logic; and a central sleep controller to:
program the sleep logic to perform at least one sleep transition for the at least one sleep block, andoperate in a first sleep mode, wherein the sleep logic is to perform the at least one sleep transition for the at least one sleep block without waking the central sleep controller from the first sleep mode. |
| 地址 |
SEATTLE WA US |
