发明名称 BUFFER FOR ORDERING OUT-OF-ORDER DATA, AND CORRESPONDING INTEGRATED CIRCUIT AND METHOD FOR MANAGING A BUFFER
摘要 A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify the memory locations containing valid data and a search circuit configured for determining a search pointer as a function of the validity signals. In the case where each memory location contains valid data, the search pointer indicates the last memory location. In the case where at least one memory location is still free, the search pointer indicates the first memory location that is free.
申请公布号 US2014185390(A1) 申请公布日期 2014.07.03
申请号 US201314143383 申请日期 2013.12.30
申请人 STMicroelectronics S.r.l. 发明人 Mangano Daniele;Rosselli Salvatore Marco;Falconeri Giuseppe
分类号 G11C7/10 主分类号 G11C7/10
代理机构 代理人
主权项 1. A buffer to order out-of-order data, comprising: a memory having N memory locations to temporarily store data; and a detection circuit configured to generate a control signal when each memory location of said N memory locations contains valid data, said detection circuit including: a first block configured to generate validity signals that identify the memory locations of said N memory locations containing valid data; anda search circuit configured to determine a search pointer as a function of said validity signals, wherein: in a first case where each memory location of said N memory locations contains valid data, said search pointer indicates a last memory location of said N memory locations; andin a second case where at least one memory location of said N memory locations is still free, said search pointer indicates a first memory location of said N memory locations that is free.
地址 Agrate Brianza IT