PARASITIC INDUCTANCE REDUCTION FOR MULTILAYERED BOARD LAYOUT DESIGNS WITH SEMICONDUCTOR DEVICES

摘要

A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer.

主权项

1. A circuit board for circuits including at least one passive device and at least one active device, comprising:
a top layer on which the passive device and the active device are mounted and electrically connected as part of a power loop, a bottom layer; and an inner layer having an electrical path connected to the top layer through vias, such that the inner layer serves as a return path of the power loop on the top layer.