| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a subtraction circuit that prevents a common mode gain from increasing with signal delay.SOLUTION: The subtraction circuit includes: transistors Mpo1 and Mno1 for determining an output voltage by a ratio of source-drain conductance therebetween; a transistor Mni1 and a resistor Ri1 for converting a voltage signal of a positive input to a current Is1; a transistor Mpc1 for producing a voltage for controlling the source-drain conductance of Mpo1 from Is1; a transistor Mni2 and a resistor Ri2 for converting a voltage signal of a negative input to a current Is2; a transistor Mnc1 for producing a voltage for controlling the source-drain conductance of Mno1 from Is2; a current mirror circuit comprising transistors Mpc2 and Mpm for applying to Mnc1 a current equivalent to Is2 flowing through Mni2 and Ri2; and a capacitor Cd for compensating for a difference in delay in reaching an output between the signal input from the positive input and the signal input from the negative input.</p> |
