| 发明名称 |
Flash Memory Interface Using Split Bus Configuration |
| 摘要 |
A system having a split bus flash memory and a method for operating the split bus flash memory is disclosed. The system may include a controller, a non-volatile memory (including first and second non-volatile memory chips) and the system bus. The controller is configured to communicate via an N-bit bus. The first and second non-volatile memory chips are configured to communicate via an M-bit bus, with M<N. The system bus connects the controller with the first and second non-volatile memory chips, wherein the system bus is split with some of the system bus lines connected to the first non-volatile memory chip and other of the system bus lines connected to the second non-volatile memory chip. In this way, the controller may communicate command, address and/or data with the memory chips in parallel. |
| 申请公布号 |
US2014189201(A1) |
申请公布日期 |
2014.07.03 |
| 申请号 |
US201313793609 |
申请日期 |
2013.03.11 |
| 申请人 |
Dhakshinamurthy Krishnamurthy;Nagabhirava Rajeev;Ahwal Tony;Agarwal Leeladhar;Dhotre Piyush Anil |
发明人 |
Dhakshinamurthy Krishnamurthy;Nagabhirava Rajeev;Ahwal Tony;Agarwal Leeladhar;Dhotre Piyush Anil |
| 分类号 |
G06F12/02 |
主分类号 |
G06F12/02 |
| 代理机构 |
|
代理人 |
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| 主权项 |
1. A controller for a non-volatile memory system comprising:
a flash memory interface comprising an N-bit bus interface configured to communicate via an N-bit bus; the controller configured to:
communicate concurrently with a first non-volatile memory chip via a first M bits of the N-bit bus and with a second non-volatile memory chip via a second M bits of the N-bit bus, the first and second non-volatile memory chips configured to communicate via an M-bit bus, with M<N, the first M bits of the N-bit bus being mutually exclusive to the second M bits of the N-bit bus. |
| 地址 |
Bangalore IN |
