| 发明名称 |
System and Method to Improve Package and 3DIC Yield in Underfill Process |
| 摘要 |
A method embodiment includes forming a packaging unit by attaching a die to a packaging substrate, applying plasma treatment to a first portion of the packaging substrate, wherein the first portion corresponds to a portion of the packaging substrate underneath the die, not applying plasma treatment to a second portion of the packaging substrate, wherein the second portion of the packaging substrate surrounds the first portion of the packaging substrate, and applying an underfill material over the first portion of the packaging substrate. |
| 申请公布号 |
US2014183760(A1) |
申请公布日期 |
2014.07.03 |
| 申请号 |
US201313836692 |
申请日期 |
2013.03.15 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
Liu Yen-Hsin;Chen Cing He;Zuo Kewei;Wang Chien Rhone |
| 分类号 |
H01L21/56;H01L23/18 |
主分类号 |
H01L21/56 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method for integrated circuit packaging comprising:
forming a packaging unit by attaching a die to a packaging substrate; applying plasma treatment to a first portion of the packaging substrate, wherein the first portion corresponds to a portion of the packaging substrate underneath the die; not applying plasma treatment to a second portion of the packaging substrate, wherein the second portion of the packaging substrate surrounds the first portion of the packaging substrate; and applying an underfill material over the first portion of the packaging substrate. |
| 地址 |
Hsin-Chu TW |
