REFERENCE SIGNAL GENERATING CIRCUIT, AD CONVERSION CIRCUIT, AND IMAGING DEVICE

摘要

A reference signal generating circuit, an AD conversion circuit, and an imaging device are provided. A clock generating unit includes a delay section including delay units, each of which delays an input signal and outputs a delayed signal, and outputs a low-order phase signal based on a signal output from the delay section. A high-order current source cell unit includes high-order current source cells, each of which generates the same constant current. A low-order current source cell unit includes low-order current source cells weighted to generate constant currents having current values that differ by a predetermined proportion of a current value of the constant current generated by the high-order current source cell. Selection of the high-order current source cell is performed based on a clock obtained by dividing a clock based on the low-order phase signal.

主权项

1. A reference signal generating circuit, comprising:
a clock generating unit that comprises a delay section including delay units, each of which delays an input signal and outputs a delayed signal, and configured to output a low-order phase signal based on a signal output from the delay section; a high-order current source cell unit that comprises high-order current source cells, each of which generates the same constant current; a low-order current source cell unit that comprises low-order current source cells weighted to generate constant currents having current values that differ by a predetermined proportion of a current value of the constant current generated by the high-order current source cell; an adding unit configured to add the constant currents output from the high-order current source cell unit and the low-order current source cell unit; and a converting unit configured to convert an electric current obtained by addition by the adding unit into a voltage, and outputs the voltage, wherein selection of the high-order current source cell is performed based on a clock obtained by dividing a clock based on the low-order phase signal, and selection of the low-order current source cell is performed based on a pulse that is generated at a time interval based on a period of the clock used for selection of the high-order current source cell and generated at a timing based on rising or falling of a clock based on the low-order phase signal.