SERDES DATA SAMPLING GEAR SHIFTER

摘要

A SerDes data sampling controller that includes a gear shifting data sampling clock that zeroes the data sampling skew at the center of the unit interval during the CDR phase lock stage, and then skews the data sample timing away from the center of the unit interval as the DFE coefficients adapt during the data transfer stage. This allows the controller to implement the best (unskewed) data sample timing during the CDR phase locking stage, and then skew the data sample timing after the DFE coefficients have adapted to provide the best (skewed) data sample timing for data bit sampling during the data transfer stage. The data sampling gear shifter may apply a variable skew value to the transition sampling or quadrature (Q) data sampling clock differentially varying the quadrature (Q) transition sampling clock from the inphase (I) data sampling clock.

主权项

1. A data sampling controller for a deserializer operative for transferring from a serial data stream into a parallel data stream, comprising:
a gear shifter configured to apply a variable time skew parameter between inphase data samples and transition samples of the serial data stream; wherein the gear shifter is configured to apply a first time skew value during a phase locking stage to cause a quadrature relation between the inphase data samples and the transition samples while the data sampling controller synchronizes to the serial data stream; and wherein the gear shifter is further configured to apply a second time skew value during a data transfer stage to cause the transition samples to track asymmetry of a serial data eye defined by the serial data stream.