| 发明名称 |
DATA OUTPUT CIRCUIT |
| 摘要 |
A data output circuit according to one embodiment of the present invention includes: a delay control block configured to generate a clock delay signal in response to a power-up signal and a reset signal; a first delay block configured to correct a duty ratio of a rising clock according to the clock delay signal and output the corrected rising clock; and a second delay block configured to correct a duty ratio of a falling clock according to the clock delay signal and output the corrected falling clock. |
| 申请公布号 |
US2014184286(A1) |
申请公布日期 |
2014.07.03 |
| 申请号 |
US201313846547 |
申请日期 |
2013.03.18 |
| 申请人 |
SK hynix Inc. |
发明人 |
CHA Jin Youp;CHO Jin Hee;KIM Jae Il |
| 分类号 |
H03K3/011 |
主分类号 |
H03K3/011 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A data output circuit comprising:
a delay control block configured to generate a clock delay signal in response to a power-up signal and a reset signal; a first delay block configured to correct a duty ratio of a rising clock according to the clock delay signal and output the corrected rising clock; and a second delay block configured to correct a duty ratio of a falling clock according to the clock delay signal and output the corrected falling clock wherein the delay control block includes a monitoring section configured to monitor skew of a PMOS transistor and an NMOS transistor of the delay control block. |
| 地址 |
Icheon-si KR |
