| 摘要 |
It has been difficult to achieve both the reduced on-resistance due to a reduced gate length, and the high element withstand voltage in a SiC DMOSFET, in the cases where a gate length is reduced for the purpose of reducing on-resistance. In the present invention, a body layer is formed after recessing a part of a source diffusion layer region after forming the source diffusion layer region. With the presence of the body layer, the distances between the source diffusion layer and respective end portions can be increased, a depletion layer is effectively expanded, and electric field concentration at the end portions can be suppressed, thereby improving withstand voltage characteristics. Consequently, the present invention can provide a silicon carbide semiconductor device that achieves both the reduced channel resistance due to a gate length reduction, and a high element withstand voltage. |
