SYSTEM AND METHOD OF ADJUSTING A CLOCK SIGNAL

摘要

A method includes receiving an input clock signal (110) at a programmable buffer (102). The method further includes filtering an output signal (112) from the programmable buffer (102) to generate a filtered signal (114) having a voltage level, where the voltage level indicates a duty cycle of the output signal (112). The method further includes comparing the voltage level (114) to a reference voltage (116). The method further includes modifying at least one operating parameter of the programmable buffer (102) to adjust the duty cycle of the output signal (112).