发明名称 METHOD AND APPARATUS FOR HANDLING DATA FLOW IN A MULTI-CHIP ENVIRONMENT USING AN INTERCHIP INTERFACE
摘要 A processing system includes an interchip interface that comprises an interchip interface module having an arbiter to allocate a dedicated time slice in every fixed number of time slices, to assign a first priority to store data item(s) from a first-type channel having a first datapath width in memory during the dedicated time slice. In the remaining time slices of the fixed number of time slices, the arbiter further arbitrates among multiple channels of one or more types other than a first type, where the multiple channels correspond to at least one datapath width different from the first datapath width, and channels with wider datapath win the arbitration. The arbiter further arbitrates among two or more channels of the same type if a certain type of channel(s) wins the arbitration in a time slice. A method for implementing the same is also disclosed.
申请公布号 US2014185593(A1) 申请公布日期 2014.07.03
申请号 US201414196804 申请日期 2014.03.04
申请人 NetLogic Microsystems, Inc. 发明人 WANG Yan
分类号 H04L5/00 主分类号 H04L5/00
代理机构 代理人
主权项 1. A method performed by a processing system that comprises at least one interchip interface module, the method comprising: assigning a first priority to a first-type communication channel in a first time slice of a set of multiple time slices based at least in part upon a criterion, the set of the multiple time slices comprising the first time slice and additional time slices; storing a first data item from the first-type communication channel in a memory element in the interchip interface module in response to at least the first priority that is assigned to the first-type communication channel; arbitrating among one or more communication channels of one or more types other than the first-type in each of the additional time slices; in response to the arbitrating, storing a second data item from one of the one or more communication channels of one or more types other than the first-type in the memory element in the interchip interface module; and repeating the assigning, the storing, and the arbitrating for one or more additional sets of multiple time slices.
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