| 摘要 |
A semiconductor device such as a power MOSFET, an IGBT or a MOS-thyristor, eg. made of SiC, having reduced electrical field at a gate oxide layer interface. In one embodiment, the device comprises a gate (36), a source (34), and a drain, wherein the gate is at least partially in contact with a gate oxide layer (40). In order to reduce an electrical field on the gate oxide layer, the device has a highly doped region (46') of a first conductivity type, eg. a P+-type region, within a JFET region (52) of a second, opposite conductivity type, eg. an N-type JFET region, being a portion of a drift region (42) of said second conductivity type, eg. an N-type drift region, located between highly doped wells (50) of said first conductivity type, eg. P+-type wells. |
