ADJUSTABLE POLE AND ZERO LOCATION FOR A SECOND ORDER LOW PASS PATH FILTER USED IN A PHASE LOCK LOOP CIRCUIT

摘要

This invention provides a loop filter device and a method for IC designers to adjust the pole or zero location of a phase lock loop (PLL) circuit. The pole and zero location are controlled by an amplifier and some on-chip resistor and capacitor components. The effective capacitance is magnified by the gain of the amplifier. The advantage of the loop filter device and the method according to embodiments of the present invention provides a feasible way to achieve a very low bandwidth in the PLL circuit without a huge external surface-mount capacitor.

主权项

1. A loop filter having an input node and an output node, the loop filter comprising:
a first resistor connected to the input node; a first capacitor coupled to the output node through the first resistor; a second capacitor coupled to the input node; a third capacitor coupled to the input node; an amplifier with a gain, comprising a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the input node through the second capacitor, the second input terminal is coupled to the input node through the third capacitor, and the output terminal is coupled to the first capacitor; a fourth capacitor coupled to the second input terminal of the amplifier and ground; an inverter having an input port and output port, the input port being coupled to a reference clock; a first NMOS transistor, a first source/drain port of the NMOS transistor being connected to an external DC bias voltage, a second source/drain port of the NMOS being connected to the first input terminal of the amplifier, a gate port of the NMOS transistor being connected to the output port of the inverter; a first PMOS transistor, a first source/drain port of the PMOS transistor being connected to the external DC bias voltage, a second source/drain port of the PMOS being connected to the first input terminal of the amplifier, a gate port of the PMOS transistor being connected to the reference clock; a second NMOS transistor, a first source/drain port of the NMOS transistor being connected to the external DC bias voltage, a second source/drain port of the NMOS being connected to the second input terminal of the amplifier, a gate port of the NMOS transistor being connected to the output port of the inverter; and a second PMOS transistor, a first source/drain port of the PMOS transistor being connected to the external DC bias voltage, a second source/drain port of the PMOS being connected to the second input terminal of the amplifier, a gate port of the PMOS transistor being connected to the reference clock.