发明名称 |
INDEPENDENT CONTROL OF PROCESSOR CORE RETENTION STATES |
摘要 |
<p>In an embodiment, a processor includes a first processor core, a second processor core, a first voltage regulator to provide a first voltage to the first processor core with a first active value when the first processor core is active, and a second voltage regulator to provide a second voltage to the second processor core with a second active value when the second processor core is active. Responsive to a request to place the first processor core in a first low power state with an associated first low power voltage value, the first voltage regulator is to reduce the first voltage to a second low power voltage value that is less than the first low power voltage value, independent of the second voltage regulator. First data stored in a first register of the first processor core is retained at the second low power value. Other embodiments are described and claimed.</p> |
申请公布号 |
WO2014105194(A1) |
申请公布日期 |
2014.07.03 |
申请号 |
WO2013US48306 |
申请日期 |
2013.06.27 |
申请人 |
INTEL CORPORATION |
发明人 |
CONRAD, SHAUN M.;GUNTHER, STEPHEN H.;SHRALL, JEREMY J.;DEVAL, ANANT S.;JAHAGIRDAR, SANJEEV S. |
分类号 |
G06F9/38;G06F1/32;G06F9/46 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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