Memory Error Detection

摘要

Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

主权项

1. A dynamic random access memory (DRAM) integrated circuit, comprising:
circuitry to receive, from a memory controller, an address with a write command that specifies a write operation; circuitry to buffer the write command for an interval of time comprising a latency associated with time to perform the write operation and an interval of time associated with detection of an error in the address; and circuitry to cause the DRAM integrated circuit to preclude the write operation from being completed if an error is determined to exist in the address within the interval of time and to complete the write operation following expiration of the latency in absence of a determination that there is an error associated with the write command.