发明名称 SYSTEM AND METHOD FOR PROVIDING UNIVERSAL SERIAL BUS LINK POWER MANAGEMENT POLICIES IN A PROCESSOR ENVIRONMENT
摘要 One particular example implementation may include an apparatus that includes logic, at least a portion of which is in hardware, the logic configured to: determine that a first device maintains a link to a platform in a selective suspend state; assign a first latency value to the first device; identify at least one user detectable artifact when a second device exits the selective suspend state; and assign, to the second device, a second latency value that is different from the first value.
申请公布号 US2014189409(A1) 申请公布日期 2014.07.03
申请号 US201213730967 申请日期 2012.12.29
申请人 Jeyaseelan Jaya L. 发明人 Jeyaseelan Jaya L.
分类号 G06F1/32 主分类号 G06F1/32
代理机构 代理人
主权项 1. An apparatus, comprising: logic, at least a portion of which is in hardware, the logic configured to: determine that a first device maintains a link to a platform in a selective suspend state;assign a first latency value to the first device;identify at least one user detectable artifact when a second device exits the selective suspend state; andassign, to the second device, a second latency value that is different from the first value.
地址 Cupertino CA US