发明名称 |
SRAM BIT-LINE AND WRITE ASSIST APPARATUS AND METHOD FOR LOWERING DYNAMIC POWER AND PEAK CURRENT, AND A DUAL INPUT LEVEL-SHIFTER |
摘要 |
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell. |
申请公布号 |
US2014185367(A1) |
申请公布日期 |
2014.07.03 |
申请号 |
US201213976326 |
申请日期 |
2012.12.27 |
申请人 |
Ngo Hieu T.;Cummings Daniel J. |
发明人 |
Ngo Hieu T.;Cummings Daniel J. |
分类号 |
G11C11/419 |
主分类号 |
G11C11/419 |
代理机构 |
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代理人 |
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主权项 |
1. An apparatus comprising:
a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. |
地址 |
Austin TX US |