发明名称 |
Cascode bias of power MOS transistors |
摘要 |
There is disclosed a driver circuit for a power amplifier of class D type having a segmented architecture with at least one current branch (22) which can be powered down in a low power mode of operation of the circuit. The branch comprising a switch with a cascode MOS transistor, the circuit further comprises a bias circuitry (31N, 31P) adapted for dynamically generating a dynamic bias control signal (DyncascN, DyncascP) so as to cause the cascode MOS transistor of the switch to be 'Off' in the low power mode. |
申请公布号 |
EP2750287(A1) |
申请公布日期 |
2014.07.02 |
申请号 |
EP20120306692 |
申请日期 |
2012.12.27 |
申请人 |
ST-ERICSSON SA |
发明人 |
BINET, VINCENT;ALLIER, EMMANUEL;AMIARD, FRANÇOIS |
分类号 |
H03F1/02;H03F3/217;H03F3/72 |
主分类号 |
H03F1/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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