Register mapping with multiple instruction sets

摘要

A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file (18) containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file (18). A first decoder (4) for the first instruction set and a second decoder (6) for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry for supporting register renaming in conjunction with a physical register file (16) and an (10) architectural register file (18).