发明名称 |
INFORMATION PROCESSING APPARATUS AND SCHEDULING METHOD |
摘要 |
An information processing apparatus includes: at least one access unit (3) that issues a memory access request for a memory (10) ; an arbitration unit (4) that arbitrates the memory access request issued from the access unit (3); a management unit (8) that allows the access unit (3) that is an issuance source of the memory access request according to a result of the arbitration made by the arbitration unit (4) to perform a memory access to the memory (10) ; a processor (2) that accesses the memory (10) through at least one cache memory (22); and a timing adjusting unit (5) that holds a process relating to the memory access request issued by the access unit (3) for a holding time set in advance and cancels the holding of the process relating to the memory access request in a case where power of the at least one cache memory (22) is turned off in the processor (2) before the holding time expires. |
申请公布号 |
EP2750043(A1) |
申请公布日期 |
2014.07.02 |
申请号 |
EP20110871370 |
申请日期 |
2011.08.23 |
申请人 |
FUJITSU LIMITED |
发明人 |
KOIKE, NOBUYUKI;MIYAMOTO, TOSHIHIRO |
分类号 |
G06F12/08;G06F13/16 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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