发明名称 Pulse output circuit, shift register, and display device
摘要 An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly.
申请公布号 US8766901(B2) 申请公布日期 2014.07.01
申请号 US201313949371 申请日期 2013.07.24
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Miyake Hiroyuki
分类号 G09G3/36 主分类号 G09G3/36
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A pulse output circuit comprising: third, fourth, fifth, eighth and ninth transistors; first, second, third and fourth input terminals; an output terminal; and third, fourth and fifth power supply lines, wherein a first electrode of the third transistor is electrically connected to the first input terminal and a second electrode of the third transistor is electrically connected to the output terminal, wherein a first electrode of the fourth transistor is electrically connected to the third power supply line and a second electrode of the fourth transistor is electrically connected to the output terminal, wherein a first electrode of the fifth transistor is electrically connected to the fourth power supply line, a second electrode of the fifth transistor is electrically connected to the gate electrode of the fourth transistor, and a gate electrode of the fifth transistor is electrically connected to the fourth input terminal, wherein a first electrode of the eighth transistor is electrically connected to the fifth power supply line, a second electrode of the eighth transistor is electrically connected to a second electrode of the ninth transistor, and a gate electrode of the eighth transistor is electrically connected to the second input terminal, and wherein a first electrode of the ninth transistor is electrically connected to the gate electrode of the fourth transistor, and a gate electrode of the ninth transistor is electrically connected to the third input terminal.
地址 Atsugi-shi, Kanagawa-ken JP