发明名称 Systems and methods for debugging in a multiprocessor environment
摘要 A method, system and apparatus for debugging in a multiprocessor environment. The system includes a principal processor which remotely debugs target programs running on a plurality of different target processors. The different types of target processors differ with respect to their instruction sets. The principal processor debugs the target programs and is configured to provide a plurality of debugging instructions specific to each instruction set, determine the type of target processor executing a target program to be debugged, select among the debugging instructions specific to each instruction set based upon the identified type of target processor, and insert the selected debugging instructions into the target program.
申请公布号 US8769495(B1) 申请公布日期 2014.07.01
申请号 US200611541983 申请日期 2006.10.02
申请人 Sony Computer Entertainment Inc. 发明人 Gupta Poorva
分类号 G06F9/44 主分类号 G06F9/44
代理机构 Lerner, David, Littenberg, Krumholz & Mentlik, LLP 代理人 Lerner, David, Littenberg, Krumholz & Mentlik, LLP
主权项 1. A method of remotely debugging target programs running on a plurality of different types of target processors, the method comprising: providing, from a principal processor in communication with the plurality of target processors, a plurality of instruction set specific debugging instructions for a plurality of different instruction sets, wherein: each target processor of the plurality of target processors is a different type of processor relative to the principal processor and having a different instruction set;at least one of the target processors of the plurality of target processors is a main-processing unit and one or more of the target processors of the plurality of target processors are sub-processing units; andthe main-processing unit monitors one or more tasks performed by the sub-processing units; executing, on the principal processor, a principal debugger; monitoring, by the principal debugger, an initiation of a target program of a shared application on a target processor of the plurality of target processors, wherein the shared application comprises a plurality of target programs that are only being executed by the plurality of target processors; communicating, from the principal debugger, with the target processor initiating the target program to determine the type of the target processor; selecting, by the principal debugger, debugging instructions from the plurality of instruction set specific debugging instructions based upon the identified type of the target processor, the selected debugging instructions are native to the instruction set of the target processor; creating, by the principal debugger, a secondary debugger for the target program; and inserting, by the secondary debugger, the selected debugging instructions into the target program.
地址 JP