Programmable cache access protocol to optimize power consumption and performance

摘要

A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring unit monitors cache misses, load use penalty, and/or other performance parameter, and compares the monitored values against a set of one or more predetermined thresholds. Based on the comparison results, a cache controller configures the programmable cache to operate in a parallel mode, to increase cache performance at the cost of greater power consumption, or in a serial mode, to conserve power at the cost of unnecessary performance. A banked cache memory that supports aligned and unaligned instruction fetches using a banked access strategy, and a cache access controller that includes a prefetch capability are also described.

主权项

1. A programmable cache, comprising:
a tag array unit to forward a result of matching tag arrays with a clock cycle delay when the programmable cache operates in a serial mode and forward the result of matching tag arrays without the clock cycle delay when the programmable cache operates in a parallel mode; a data array unit to generate one of a single data array cache line and multiple data array cache lines based on a configurable control parameter; and a cache controller to configure the tag array unit and the data array unit to operate in either the parallel mode or the series mode based on the configurable control parameter.