Processor with increased efficiency via early instruction completion

摘要

Methods and apparatuses are provided for increased efficiency in a processor via early instruction completion. An apparatus is provided for increased efficiency in a processor via early instruction completion. The apparatus comprises an execution unit for processing instructions and determining whether a later issued instruction is ready for completion or an earlier issued instruction is ready for completion and a retire unit for retiring the later issued instruction when the later instruction is ready for completion or to retire the earlier instruction when later instruction is not ready for completion and the earlier issued instruction has a known good completion status. A method is provided for increased efficiency in a processor via early instruction completion. The method comprises completing an earlier issued instruction having a known good completion status ahead of a later issued instruction when the later issued instruction is not ready for completion.

主权项

1. A method, comprising:
determining one or more early completion times for instructions that are capable of early completion and creating a separate first-in-first-out (FIFO) table for each of the instructions, the FIFO table comprising the one or more early completion times for the corresponding instruction; forwarding an earlier issued instruction having a known good completion status out of an execution pipeline of a processor ahead of a later issued instruction having an unknown completion status when at least one of the early completion times from the FIFO table for the earlier issued instruction has occurred.