System and method for efficient modeling of NPskew effects on static timing tests

摘要

A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.

主权项

1. A computer-implemented method that simulates NPskew effects on a combination semiconductor device using slew perturbations, said combination semiconductor device comprising an NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor), said method comprising:
performing a timing test comprising one of a pulse width test and an inactive test, by a computing device, by:
evaluating, by said computing device, perturbed slew times for a combination semiconductor device comprising a relatively strong NFET/relatively weak PFET, producing a first timing test result;evaluating, by said computing device, perturbed slew times for a combination semiconductor device comprising a relatively weak NFET/relatively strong PFET, producing a second timing test result; andevaluating, by said computing device, unperturbed slew times for a combination semiconductor device having a balanced NFET/PFET, producing a third timing test result; determining, by said computing device, which evaluation of said perturbed and unperturbed slew times produces a timing test result having the smallest value from said first timing test result, said second timing test result and said third timing test result, for said combination semiconductor device; and outputting a NPskew effect adjusted timing test result based on said determining said timing test result having the smallest value.