Multi-port memory and operation

摘要

Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications.

主权项

1. A memory, comprising:
two or more ports, each port comprising one or more regions of memory and control circuitry for controlling access to the one or more regions of memory in response to commands; and at least one interport control bus for communicating commands between the control circuitry of two of more of the ports; wherein the control circuitry of a first port of the two or more ports is configured to select whether to respond to commands received from either a first external control bus that is different than the at least one interport control bus or the at least one interport control bus; and wherein the control circuitry of a second port of the two or more ports is configured to select whether to respond to commands received from either a second external control bus that is different than the at least one interport control bus and the first external control bus or the at least one interport control bus.