发明名称 Voltage regulator circuit and semiconductor device, including transistor using oxide semiconductor
摘要 A voltage regulator circuit includes a transistor and a capacitor. The transistor includes a gate, a source, and a drain, a first signal is inputted to one of the source and the drain, a second signal which is a clock signal is inputted to the gate, an oxide semiconductor layer is used for a channel formation layer, and an off-state current is less than or equal to 10 aA/μm. The capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a high power source voltage and a low power source voltage are alternately applied to the second electrode.
申请公布号 US8766608(B2) 申请公布日期 2014.07.01
申请号 US201012909629 申请日期 2010.10.21
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Yamazaki Shunpei;Koyama Jun;Takahashi Kei;Tsubuku Masashi;Noda Kosei
分类号 G05F1/00;H01L27/14 主分类号 G05F1/00
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A voltage regulator circuit comprising: a transistor comprising a gate, a source, a drain, an oxide semiconductor layer used for a channel formation layer of the transistor, and a conductor layer; and a capacitor comprising a first electrode and a second electrode, wherein a first signal is inputted to one of the source and the drain of the transistor, wherein a second signal which is a clock signal is inputted to the gate of the transistor, wherein an off-state current of the transistor is less than or equal to 10 aA/μm, wherein the first electrode of the capacitor is electrically connected to the other of the source and the drain of the transistor, wherein a high power source voltage and a low power source voltage are alternately applied to the second electrode of the capacitor, wherein a first voltage of the first signal is stepped up or down to obtain a third signal, wherein the third signal which has a second voltage obtained by stepping up or down the first voltage of the first signal is outputted as an output signal through the other of the source and the drain of the transistor, wherein the gate and the oxide semiconductor layer overlap with each other with a first insulating layer therebetween, wherein the conductor layer and the oxide semiconductor layer overlap with each other with a second insulating layer therebetween, and wherein the oxide semiconductor layer is between the first insulating layer and the second insulating layer.
地址 Atsugi-shi, Kanagawa-ken JP