Reducing the effect of elements mismatch in a SAR ADC

摘要

An intermediate set of bits of a SAR ADC are converted into first intermediate analog value and a second intermediate analog value respectively from a first set of representative capacitor and a second set of representative capacitor. A capacitor in the first set and second set are selected as not same. A SAR ADC output code is generated from the first intermediate analog value and the second intermediate analog value. The resolution of a N bit SAR ADC can be enhanced by generating more than one N bits digital codes correspondingly operating the N Bit SARADC with more than on transfer functions. Each transfer function is selected such that they are offset by a fraction of LSB value. The more than one N bits digital codes are then added to form P bits digital code such that P is greater than N due to addition.

主权项

1. A method comprising:
generating an intermediate set of bits; converting the intermediate set of bits to a first intermediate analog value from a first set of representative capacitors from a plurality of capacitors in a successive approximation register (SAR) analog-to-digital converter (ADC); converting the intermediate set of bits to a second intermediate analog value from a second set of representative capacitors from the plurality of capacitors in the SAR ADC; and generating a plurality of digital code bits from the first intermediate analog value and the second intermediate analog value, wherein more than one capacitor in the second set of representative capacitors and the first set of representative capacitors are not same, wherein the plurality of capacitor further comprises plurality of capacitor banks of equal capacitance value with each capacitor bank being placed at different location on a semiconductor die and the first set of representative capacitors and the second set of representative capacitor are formed by coupling a set of banks to a reference voltage.