E-fuse array circuit

摘要

An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.

主权项

1. An e-fuse array circuit, comprising:
a first gate insulation layer formed over a substrate; a program gate formed over the first gate insulation layer; a second gate insulation layer formed on an internal surface of a trench that is formed by etching the substrate; and a word line gate filling the trench where the second gate insulation layer is formed.