| 摘要 |
A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals. |
| 主权项 |
1. A power MOSFET package, comprising:
a semiconductor substrate having a first surface and an opposite second surface, wherein the semiconductor substrate has a first conductivity type and forms a drain region; a doped region extending downward from the first surface, the doped region having a second conductivity type; a source region located in the doped region, the source region having the first conductivity type; a gate formed overlying the first surface or buried under the first surface, wherein a gate dielectric layer is located between the gate and the semiconductor substrate; a first conducting structure located overlying the semiconductor substrate and having a first terminal, the first conducting structure electrically connected to the drain region; a second conducting structure located overlying the semiconductor substrate and having a second terminal, the second conducting structure electrically connected to the source region; a third conducting structure located overlying the semiconductor substrate and having a third terminal, the third conducting structure electrically connected to the gate, wherein the first terminal, the second terminal, and the third terminal are substantially coplanar; and a protection layer located between the semiconductor substrate and the first terminal, the second terminal, and the third terminal. |
