Parallel Processing of a Sequential Program Using Hardware Generated Threads and Their Instruction Groups Executing on Plural Execution Units and Accessing Register File Segments Using Dependency Inheritance Vectors Across Multiple Engines

摘要

A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instruction formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.

主权项

1. A system, comprising:
a cache adapted to store a prefeteched value corresponding to a consuming instruction, wherein the prefeteched value has a corresponding name and wherein the consuming instruction explicitly references the corresponding name instead of a memory address; an execution unit to execute the consuming instruction in conjunction with the prefetched value; and a scheduling unit to issue the consuming instruction after the prefetched value is loaded in the cache and to release the location of the prefeteched value in the cache after the execution unit executes the consuming instruction.