CIRCUIT FOR SENSING MLC FLASH MEMORY

摘要

A circuit for sensing a multi-level cell (MLC) flash memory is disclosed. The circuit comprises a plurality of first decoding units, a second decoding unit and a data latch. Each of the first decoding units provides a timing information and includes a controlled transistor to allow a current to pass therethrough, and a capacitor to be charged by the current or to discharge through the controlled transistor. The second decoding unit provides a latch signal and includes a controlled transistor to allow a current to pass therethrough, the magnitude of the current being associated with data in an MLC, and a capacitor to be charged by the current or to discharge through the controlled transistor. The data latch, in response to the timing information from each of the first decoding units and the latch signal from the second decoding unit, determines the data in the MLC.

主权项

1. A circuit for sensing a multi-level cell (MLC) flash memory, the circuit comprising:
a plurality of first decoding units each providing a timing information and including:
a controlled transistor to allow a current to pass therethrough; anda capacitor to be charged by the current or to discharge through the controlled transistor; a second decoding unit providing a latch signal and including:
a controlled transistor to allow a current to pass therethrough, the magnitude of the current being associated with data in an MLC; anda capacitor to be charged by the current or to discharge through the controlled transistor; and a data latch, in response to the timing information from each of the first decoding units and the latch signal from the second decoding unit, to determine the data in the MLC.