PARALLEL PROCESSING USING MULTI-CORE PROCESSOR

摘要

Disclosed are methods, systems, paradigms and structures for processing data packets in a communication network by a multi-core network processor. The network processor includes a plurality of multi-threaded core processors and special purpose processors for processing the data packets atomically, and in parallel. An ingress module of the network processor stores the incoming data packets in the memory and adds them to an input queue. The network processor processes a data packet by performing a set of network operations on the data packet in a single thread of a core processor. The special purpose processors perform a subset of the set of network operations on the data packet atomically. An egress module retrieves the processed data packets from a plurality of output queues based on a quality of service (QoS) associated with the output queues, and forwards the data packets towards their destination addresses.

主权项

1. A method comprising:
receiving, at an ingress module of a network processor, a data packet from a computer network, the data packet to be processed by one of a plurality of core processors of the network processor; storing, in a memory having a plurality of buffers, the data packet in the memory, the storing including storing distinct portions of the data packet in one or more buffers if the packet size exceeds a size of a buffer; and generating a packet buffer chain for the data packet, the generating including
creating a plurality of packet buffer structures for the data packet, wherein one of the packet buffer structures is a header packet buffer structure corresponds to a first buffer of the one or more buffers containing a first portion of the data packet, and wherein another one of the packet buffer structures is a tail packet buffer structure that corresponds to a last buffer of the one or more buffers containing a last portion of the data packet, andlinking each of the packet buffer structures from the header packet buffer structure to the tail packet buffer structure.