GUARDBAND REDUCTION FOR MULTI-CORE DATA PROCESSOR

摘要

A multi-core data processor includes multiple data processor cores and a power controller. Each data processor core has a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal. The power controller is coupled to each of the data processor cores for providing the clock signal and the power supply voltage to each of the data processor cores. The power controller provides at least one of the clock signal and the power supply voltage to an active one of the data processor cores in dependence on a number of idle signals received from the data processor cores.

主权项

1. A multi-core data processor comprising:
a plurality of central processing unit (CPU) core modules, each having a first input for receiving a clock signal, a second input for receiving a power supply voltage, and an output for providing an idle signal; and a clock and power controller coupled to each of said plurality of CPU core modules for providing said clock signal and said power supply voltage to each of said plurality of CPU core modules, said clock and power controller providing at least one of said clock signal and said power supply voltage to an active one of said plurality of CPU core modules in dependence on a number of idle signals received from said plurality of CPU core modules.