| 摘要 |
<p>A resistive memory device includes a memory cell array, a dynamic random access memory (DRAM) interface, and a read sensing circuit. The memory cell array includes a plurality of resistive memory cells connected to each of a plurality of word lines and a plurality of bit lines. The DRAM interface performs the communications with a memory controller. The read sensing circuit is connected to the bit lines, performs a precharge operation between a point receiving an active command via the DRAM interface and a point receiving a read command, and senses data from the resistive memory cells to provide read data.</p> |
