发明名称 |
Methods and Systems for Enhancing Hardware Transactions Using Hardware Transactions in Software Slow-Path |
摘要 |
Hybrid transaction memory systems and accompanying methods. A transaction to be executed is received, and an initial attempt is made to execute the transaction in a hardware path. Upon a failure to successfully execute the transaction in the hardware path, an attempt is made to execute the transaction in a hardware-software path. The hardware-software path includes a software path and at least one hardware transaction. |
申请公布号 |
US2014181821(A1) |
申请公布日期 |
2014.06.26 |
申请号 |
US201314136824 |
申请日期 |
2013.12.20 |
申请人 |
Massachusetts Institute of Technology |
发明人 |
Shavit Nir N.;Matveev Alexander |
分类号 |
G06F9/46 |
主分类号 |
G06F9/46 |
代理机构 |
|
代理人 |
|
主权项 |
1. A system, comprising:
at least one processor; and at least one memory storing computer-executable instructions that, when executed by the at least one processor, configure the system to:
receive a transaction to be executed;initially attempt to execute the transaction in a hardware path; andupon a failure to successfully execute the transaction in the hardware path, attempt to execute the transaction in a hardware-software path, wherein the hardware-software path comprises a software path and at least one hardware transaction. |
地址 |
Cambridge MA US |