发明名称 PLATFORM POWER CONSUMPTION REDUCTION VIA POWER STATE SWITCHING
摘要 Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.
申请公布号 US2014181560(A1) 申请公布日期 2014.06.26
申请号 US201314139864 申请日期 2013.12.23
申请人 Muralidhar Rajeev D.;Seshadri Harinarayanan;Rudramuni Vishwesh M.;Quinzio Richard;Fiat Christophe;Zayet Aymen;Singh Youvedeep;Mansoor Illyas M. 发明人 Muralidhar Rajeev D.;Seshadri Harinarayanan;Rudramuni Vishwesh M.;Quinzio Richard;Fiat Christophe;Zayet Aymen;Singh Youvedeep;Mansoor Illyas M.
分类号 G06F1/32 主分类号 G06F1/32
代理机构 代理人
主权项 1. An apparatus comprising: control logic, the control logic at least partially comprising hardware logic, to cause a processor to enter a first low power consumption state instead of a second low power consumption state based on a threshold time period between a first wake event and a second wake event, wherein the first low power consumption state is to consume more power than the second low power consumption state.
地址 Bangalore IN